Stalling CPU pipeline to prevent corruption in trace while maintaining coherency with asynchronous events
US7099817B2 · kind B2 · utility
4Cited by
3References
4Claims
0Family size
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Key dates
| Filing date | Nov 22, 2002 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Oct 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3636
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of preventing trace data first-in-first-out buffer overflow in a pipelined data processor stops new instructions when a trace data first-in-first-out buffer is in danger of overflowing. The method also stalls a predetermined number of pipeline stages in the pipeline ahead of the first pipeline stage. The trace data first-in-first-out buffer is emptied while the pipeline is stalled. On restart, the stalled pipeline stages are restarted ahead of re-enabling new instructions. Asynchronous trigger events received during the stall may be buffered and unrolled in order or merely stored and applied simultaneously on restart.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.