Method for reducing an importance level of a cache line
US7099998B1 · kind B1 · utility
4Cited by
9References
38Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing an importance level of a line in a memory of a cache. An instruction is provided to the cache, the instruction indicating that the line is a candidate for replacement. The importance level of the line may then be reduced based on the instruction. The method may increase cache hit rate and, hence, microprocessor performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.