Memory stack architecture for reduced TLB misses
US7100014B2 · kind B2 · utility
2Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2003 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Aug 12, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99956
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment disclosed relates to a computer system. The computer system includes a microprocessor, an operating system, and a memory system. The microprocessor includes a register stack and a register stack engine (RSE), and the operating system includes a kernel. The memory system is configured to have a single memory page that includes both a kernel stack and an RSE stack. The memory system may be further configured such that the kernel stack and the RSE stack grow in opposite directions and such that a uarea data structure is located between those two stacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.