Patent · US Expired

Controlling the timing of test modes in a multiple processor system

US7100033B2 · kind B2 · utility

8Cited by

7References

15Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Charles P. Roth · Austin, US
Minesh S. Desai · Chandler, US
Gerold Mueller · Ulm, DE
Peter Lachner · Heroldstatt, DE

Key dates

Filing date	Oct 23, 2002
Grant date	Aug 29, 2006
Priority date	—
Expiry date	Dec 6, 2023

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/2273
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system includes a first processor, a second processor and a circuit. The first processor includes a first terminal and enters a first test mode in response to the first terminal having a first signal state. The second processor includes a second terminal. The second processor enters a second test mode in response to the second terminal having a second signal state. The circuit may regulate the timing of the first and second signal states to place both the first processor in the first test mode and the second processor in the second test mode at approximately the same time. The circuit may regulate the timing of the signals to cause the first and second processors to resume normal modes of operation at approximately the same time.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.