Impedance matching circuit design method
US7100127B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2003 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Dec 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for designing an impedance matching circuit. The impedance matching circuit is for matching a power amplifier and an antenna circuit. The antenna circuit originally includes an antenna and a first antenna impedance matching circuit. For suiting the design modification of the power amplifier, the method provides a second antenna impedance matching circuit, and matches it with a first power amplifier impedance matching circuit to constitute an overall circuit. The impedance of the overall circuit forms a first locus on the Smith Chart, and is made to have a phase error meeting a predetermined specification. Next, the second power amplifier impedance matching circuit is designed and matched with the first antenna impedance matching circuit to constitute another overall circuit. And the impedance of this overall circuit forms a second locus on the Smith Chart. As the second locus overlaps the first locus, the system has a phase error meeting a predetermined specification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.