Secure attention instruction central processing unit and system architecture
US7100205B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 22, 2003 |
| Grant date | Aug 29, 2006 |
| Priority date | — |
| Expiry date | Oct 22, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/57
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A central processing unit comprising means for processing computer instructions. The Means for processing computer instructions includes means for receiving computer instructions and means for executing computer instructions. A secure memory unit is coupled to the processing means, and contains one or more resident security check programs therein. When the means for processing information receives a secure attention instruction through the receiving means the means for executing computer instructions interrupts the instructions it is executing, and executes the security check program by retrieving its instructions from the secure memory. The security check program returns the result of the check program. If the results are satisfactory, a cryptographic check key authenticates the result values transmitted to the source of the secure attention instruction. If the cryptographic check value is incorrect or non-existent, the source of the secure attention instruction is notified of a security problem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.