Electronic devices comprising bottom-gate TFTs and their manufacture
US7101740B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 25, 2003 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Jul 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6745
Abstract
A method of manufacturing an electronic device comprising a bottom-gate TFT (12) is provided, the method comprising the steps of: forming a doped amorphous silicon gate layer (26′) on a substrate, the gate layer defining a gate (26), forming a gate insulating layer (32) over the gate, forming an amorphous silicon active layer (28′) over the gate insulating layer and overlying at least part of the gate, and annealing the amorphous silicon active layer to form a polysilicon active layer (28). A thinner gate insulating layer can be used giving a TFT having a low threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.