Thin film transistor array panel for display and manufacturing method thereof
US7102168B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2002 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Jan 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A gate wire including a gate line, a gate pad and a gate electrode is formed on a substrate. A gate insulating layer, a semiconductor layer, a doped amorphous silicon layer and a conductive layer are deposited in sequence, and then a photoresist film pattern is formed thereon. The photoresist film pattern includes a first portion positioned between a source electrode and a drain electrode, a second portion thicker than the first portion, and the third portion with no photoresist. A data wire including a data line, a data pad, a source electrode, a drain electrode and a conductor pattern for storage capacitor, an ohmic contact layer pattern and a semiconductor pattern are formed by etching the conductive layer, the doped amorphous silicon layer and the semiconductor layer using the photoresist film pattern. A plurality of color filters of red, green and blue having apertures exposing part of the drain electrode are formed thereon. A passivation layer made of acryl-based organic material having excellent planarization characteristic is formed thereon. A pixel electrode, an auxiliary gate pad and an auxiliary data pad connected to the drain electrode, the gate pad and the data pad via…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.