High reliability electrically erasable and programmable read-only memory (EEPROM)
US7102188B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2005 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Apr 5, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EEPROM cell that combines a FET transistor and a capacitor. The transistor has a well that is shared by potentially all of the EEPROM cells in the array thereby reducing size. A gate terminal is formed over the well. Source and drain terminals are formed in the well. The well is isolated from the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal, and may be oppositely doped from the gate terminal to improve retention. The second terminal is formed by a second well that is underneath the first terminal and isolated from the first terminal. The capacitance may be increased without area increase by forming a metal layer over the first terminal and separated from the first terminal by a thick dielectric layer, and connected to the second well via a conductive via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.