Passive element chip and manufacturing method thereof, and highly integrated module and manufacturing method thereof
US7102227B2 · kind B2 · utility
7Cited by
4References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 30, 2004 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Jan 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A passive element chip permits a reduced size and a higher packaging density to be achieved. The passive element chip has a substrate, a plurality of passive elements formed by metal wires on the substrate, and electrodes for electrically connecting the plurality of passive elements to an external source. The passive elements are isolated from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.