Voltage translator with data buffer
US7102389B2 · kind B2 · utility
3Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2004 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Dec 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage translator with data buffer includes an input inverter receiving a data input signal at a first voltage level. A level shifting cross-coupled NOR circuit is coupled to the input inverter for translating the data input signal at a second voltage level. An output stage driven by the level shifting cross-coupled NOR circuit for providing a data output signal at the second voltage level. The voltage translator enables improved performance across various power, voltage and temperature (PVT) conditions and reliably reduces or minimizes shoot through current and delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.