Circuit to manage and lower clock inaccuracies of integrated circuits
US7102402B2 · kind B2 · utility
8Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 2002 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Mar 11, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for generating and distributing highly accurate and stable clocks on a large integrated die is described. A Digital De-skew System is used to help prevent metastability and dither, provide a wide controllable delay range, and alternate sampling of phase detectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.