Integral wiring harness
US7102624B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2005 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Apr 27, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24926
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a touch panel wherein a glass substrate is coated with a resistive layer; a pattern of conductive edge electrodes and a conductive wire trace pattern are applied to the resistive layer; the conductive edge electrodes are electrically isolated from the conductive wire traces; and a protective insulative border layer is applied over the edge electrodes and the wire traces. A touch panel which includes a glass substrate coated with a resistive layer on one surface thereof; a pattern of edge electrodes on the resistive layer; a wire trace pattern on the resistive layer; a trench in the resistive layer between the wire trace pattern and the edge electrode pattern; and a protective insulative border layer over the edge electrode pattern and the wire traces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.