Latch-up-free ESD protection circuit using SCR
US7102864B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2004 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Mar 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/713
Abstract
A latch-up-free ESD protection circuit using SCR is disclosed, in which an SCR is connected between the input pad and the negative power supply; a turn-on switch and a turn-off switch are connected between the positive power supply VDD (or the input pad) and the SCR; and a transistor gating circuit is connected to the turn-on switch and the turn-off switch to direct the operation of the SCR. When overvoltage stress develops over the input pad in the fast-transient mode, the turn-on switch enables the NPN transistor to switch on the SCR to form a discharging path for electrostatic discharge; and when overvoltage stress is released, the turn-off switch enables the PNP transistor to switch off the SCR, thus making it immune to any latch-up after the overvoltage stress is released, and having the advantages of fast triggering, low trigger voltage, no latch-up, and full ESD protection in the active and passive modes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.