Memory package
US7102883B2 · kind B2 · utility
1Cited by
9References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2003 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Sep 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/186
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory package comprising a first circuit board having a plurality of memory element sockets and a second circuit board coupled to the first circuit board and comprising a controller chip. The first and second circuit boards are disposed within a tray having a base and two sides. A handle is connected to the tray such that the handle is pivotal with respect to the tray. The handle has a lever system and latch that is slidably engaged with the lever system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.