Stacked memory, memory module and memory system
US7102905B2 · kind B2 · utility
64Cited by
3References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2004 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Nov 10, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A point-to-point bus and a daisy chain bus are provided for supplying signals to stacked memories, and the stacked memories are mounted mutually apart by a distance equivalent to the length of the stacked memory on both surfaces of a module substrate. Furthermore, the memory chips arranged in a stacked memory mounted on one surface are set in an active state at the same time alternately with the memory chips arranged in a stacked memory mounted on another surface of the module substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.