Scheduling the dispatch of cells in multistage switches using a hierarchical arbitration scheme for matching non-empty virtual output queues of a module with outgoing links of the module
US7103056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Oct 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/1569
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multiple phase cell dispatch scheme, in which each phase uses a simple and fair (e.g., round robin) arbitration methods, is described. VOQs of an input module and outgoing links of the input module are matched in a first phase. An outgoing link of an input module is matched with an outgoing link of a central module in a second phase. The arbiters become desynchronized under stable conditions which contributes to the switch's high throughput characteristic. Using this dispatch scheme, a scalable multiple-stage switch able to operate at high throughput, without needing to resort to speeding up the switching fabric and without needing to use buffers in the second stage, is possible. The cost of speed-up and the cell out-of-sequence problems that may occur when buffers are used in the second stage are therefore avoided. A hierarchical arbitration scheme used in the input modules reduces the time needed for scheduling and reduces connection lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.