Scalable 2-stage interconnections
US7103059B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2002 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Dec 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/15
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Modifications to the 2-stage interconnection to allow flexible scalability. Different switching fabrics having a range of different sizes can be constructed out of the same set of I/O switching nodes through this modified 2-statge interconnection, which can further be recursively invoked to construct large switching fabrics with desirable sizes. The recursive construction incorporating the modified 2-stage interconnection can seamlessly be realized through the five hierarchical levels of physical implementation, including inside-chip implementation, PCB implementation, orthogonal packaging, interface-board packaging and fiber-array packaging. The routability of the resulting switching fabric is always guaranteed and self-routing mechanism is also pertained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.