System and method for half-rate clock phase detection
US7103131B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2002 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Jan 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method for half-rate phase detecting are provided. The method comprises: receiving binary data; dividing the data by two; latching the divided data with a first half-rate clock, creating Q1; latching the divided data with a second half-rate clock, the inverse of the first clock, creating Q2; latching Q1 with the second clock, creating Q3; latching Q2 with the first clock, creating Q4; XORing Q1 and Q2 to create phase signals; and, XORing Q3 and Q4 to create reference signals, corresponding to the phase signals. In some aspects of the method, dividing the stream of data by two introduces a processing delay into the divided data. Then, the method further comprises: in response to the phase and reference signals, phase-locking a voltage controlled oscillator to generate the first and second clocks; delaying the received stream of binary data; and, using the first and second clocks to sample the delayed binary data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.