Processor efficient transformation and lighting implementation for three dimensional graphics utilizing scaled conversion instructions
US7103621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2003 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Aug 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Efficient techniques for computation of texture coordinates using scaled conversion operations for a 3D graphics pipeline utilizing a scaled floating point to integer instruction and a scaled integer to floating point instruction to significantly reduce memory requirements. A parallel array VLIW digital signal processor is employed along with specialized scaled conversion instructions and communication operations between the processing elements, which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the graphics pipeline hardware to be efficiently used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.