Method for designing semiconductor circuit device, utilizing boundary cells between first and second circuits driven by different power supply systems
US7103866B2 · kind B2 · utility
3Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2004 |
| Grant date | Sep 5, 2006 |
| Priority date | — |
| Expiry date | Oct 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To design a chip having a plurality of circuit areas driven by different power supplies, a boundary cell to be inserted on the boundary between the circuit areas is prepared. After creating a logic circuit netlist with a design tool, the boundary cell is inserted on the boundary. The boundary cell is connected on a signal transmission path between the circuit areas. A circuit for suppressing shoot-through current or leakage current is used as the boundary circuit. By preparing the boundary cell in a cell library, chip design is facilitated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.