Method of manufacturing MOS transistor
US7105414B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2004 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | Dec 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a MOS transistor capable of suppressing a short channel effect by suppressing boron (B) ion diffusion in the MOS transistor. The method includes steps of: forming an impurity diffusion suppressing layer in an active region of a semiconductor substrate; forming an impurity layer containing boron ions in a lower portion of the impurity diffusion suppressing layer; and thermally treating on the substrate, wherein the impurity diffusion suppressing layer suppresses diffusion of the boron ions during the thermal treatment step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.