Clock adjustment
US7106111B2 · kind B2 · utility
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2References
42Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 12, 2004 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | Nov 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits and methods are provided for clock adjustment. A method for clock adjustment includes receiving feedback clocks from independent ASIC modules. The method includes comparing the feedback clocks to a reference clock to generate phase measurement values. A common delay is removed from the phase measurement values to form normalized correction values. Target phase values and clock select values are selected using the normalized correction values. And, clock signals to independent ASIC modules are adjusted based on the target phase values and clock select values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.