Calibratable phase-locked loop
US7106140B2 · kind B2 · utility
6Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 20, 2003 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | May 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0898
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The subject matter hereof relates to a calibratable phase-locked loop. The calibratable phase-looked loop in an example embodiment comprises a charge pump and calibration means for the loop, wherein calibration means comprises: first means for rendering unstable a stable phase-locked loop so that a sinusoidal signal is provided; second means for generating a squared signal from the so-provided sinusoidal signal; and a logic circuit for determining the frequency of the squared signal and for controlling the charge pump in correcting the frequency of the squared signal as a function of a desired frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.