Defect management enabled PIRM and method
US7106639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2004 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | Sep 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A defect management enabled PIRM including a data storage medium providing a plurality of cross point data storage arrays. Each array provides a plurality of memory cells. The arrays are allocated into separate super arrays, the separate super arrays virtually aligned as sets. A controller is also provided, capable of establishing the selection of a virtually aligned set of arrays and a virtually aligned set of memory cells. The controller is operable during a write operation to receive a word of data bits and detect a defective array in the selected virtually aligned set of memory arrays. The controller is further capable of directing the allocation of at least one data bit from the defective memory array to a spare memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.