System and method for accelerated clock synchronization of remotely distributed electronic devices
US7106823B2 · kind B2 · utility
4Cited by
3References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 15, 2002 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | Dec 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0664
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A timing recovery system and method for accelerated clock synchronization of remotely distributed electronic devices is provided. The system includes a phase locked loop, a linear estimator and control logic. The method includes sampling a clock signal received from an electronic device, applying a linear estimation technique to estimate the frequency and phase of the received signal and providing those estimates to a phase locked loop to accelerate the phase locked loop acquisition rate and secure signal lock quickly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.