Finite impulse response filter algorithm for implementation on digital signal processor having dual execution units
US7107302B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2000 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | May 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2218/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.