Memory bus arbitration using memory bank readiness
US7107386B1 · kind B1 · utility
14Cited by
6References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2004 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | Jan 15, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.