Apparatus for capturing data on a debug bus
US7107394B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2003 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | Oct 26, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/273
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus is disclosed for capturing data on a debug bus comprising N registers connected in a ring, wherein data is clocked from one register to the next in the ring in only one direction. The apparatus comprises a counter that increments by one each time data is clocked from one register to the next; and logic for comparing a value of the counter with a preselected register address on each count of the counter, wherein the logic for comparing comprises a comparator having an input connected to receive the preselected register address, an input connected to receive the value of the counter, and an output operable to drive a select signal of a multiplexer provided for capturing data from the debug bus at an extraction point when the counter value is equal to the preselected register address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.