System and method for preventing data corruption in solid-state memory devices after a power failure
US7107480B1 · kind B1 · utility
349Cited by
13References
14Claims
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Key dates
| Filing date | Dec 20, 2001 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | May 11, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data preservation system for flash memory systems with a host system, the flash memory system receiving a host system power supply and energizing an auxiliary energy store therewith and communicating with the host system via an interface bus, wherein, upon loss of the host system power supply, the flash memory system actively isolates the connection to the host system power supply and isolates the interface bus and employs the supplemental energy store to continue write operations to flash memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.