Test apparatus for semiconductor device
US7107504B2 · kind B2 · utility
5Cited by
5References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2002 |
| Grant date | Sep 12, 2006 |
| Priority date | — |
| Expiry date | Apr 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A test apparatus for a semiconductor device, which improves the reliability of an operational test on target devices on a wafer using BOST (Built Out Self Test) and BIST (Built In Self Test). The test apparatus includes an external test unit, the BIST circuit formed in the semiconductor device, and BOST device which is coupled between the external test unit and the semiconductor device. Pattern data for a pattern dependency test is stored in the BIST circuit and pattern data for a timing dependency test is stored in the BOST device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.