Wafer-level opto-electronic testing apparatus and method

US7109739B2 · kind B2 · utility

Assignee

• SiOptical, Inc. · US

Inventors

• Prakash Gothoskar · Allentown, US
• Margaret Ghiron · Allentown, US
• Robert Keith Montgomery · Easton, US
• Vipulkumar Patel · Emmaus, US
• Kalpendu Shastri · Orefield, US
• Soham Pathak · Allentown, US
• David Piede · Allentown, US
• Katherine A. Yanushefski · Emmaus, US

Key dates

• Filing date: Mar 8, 2005
• Grant date: Sep 19, 2006
• Expiry date: Mar 8, 2025

Classification

• Technology area (CPC G): Physics
• CPC primary: G02B2006/12107
• WIPO field: Optics
• WIPO sector: Instruments

Abstract

A wafer-level testing arrangement for opto-electronic devices formed in a silicon-on-insulator (SOI) wafer structure utilizes a single opto-electronic testing element to perform both optical and electrical testing. Beam steering optics may be formed on the testing element and used to facilitate the coupling between optical probe signals and optical coupling elements (e.g., prism couplers, gratings) formed on the top surface of the SOI structure. The optical test signals are thereafter directed into optical waveguides formed in the top layer of the SOI structure. The opto-electronic testing element also comprises a plurality of electrical test pins that are positioned to contact a plurality of bondpad test sites on the opto-electronic device and perform electrical testing operations. The optical test signal results may be converted into electrical representations within the SOI structure and thus returned to the testing element as electrical signals.