Delay-locked loop (DLL) integrated circuits that support efficient phase locking of clock signals having non-unity duty cycles
US7109760B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Jun 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Delay-locked loop (DLL) integrated circuits include digital phase comparators that are unaffected by variable duty cycle ratios. These phase comparators determine a shortest direction to phase lock before establishing a value of a compare signal (COMP) that specifies the shortest direction. The phase comparator is responsive to a reference clock signal REF and a feedback clock signal FB. These clock signals have equivalent periods and may have equivalent non-unity duty cycle ratios. The phase comparator is configured to determine whether a first degree to which the reference clock signal REF leads the feedback clock signal FB is smaller or larger than a second degree to which the reference clock signal REF lags the feedback clock signal FB. Based on this determination, the phase comparator generates a compare signal COMP that identifies a direction in time the feedback clock signal FB should be shifted to bring it into alignment with the reference clock signal REF. This direction represents a speed-up direction when the first degree is determined to be less than the second degree or a slow-down direction when the second degree is determined to be less than the first degree.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.