Electronic shutter using buried layers and active pixel sensor and array employing same
US7110028B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 13, 2002 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Mar 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/1825
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An electronic shutter switching transistor for a CMOS electronic is formed in a semiconductor substrate of a first conductivity type. The transistor comprises a pair of spaced apart doped regions of a second conductivity type opposite the first conductivity type disposed in the semiconductor substrate forming source/drain regions. A gate is disposed above and insulated from the semiconductor substrate and is self aligned with the pair of spaced apart doped regions. A well of the second conductivity type laterally surrounds the pair of spaced apart doped regions and extends deeper into the substrate than the doped regions. A buried layer of the second conductivity type underlies and is in contact with the well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.