ESD protection circuit and display panel using the same
US7110229B2 · kind B2 · utility
9Cited by
4References
3Claims
0Family size
Inventors
Key dates
| Filing date | May 7, 2004 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Jan 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136204
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An ESD protection circuit for low temperature poly-silicon thin film transistor panel and a display panel using the same. The feature of the ESD protection circuit comprises an ESD detection circuit disposed between a first power line and a second power line, for outputting an enable signal when an ESD event occurs in the first power line; and a discharge device having a control terminal coupled to the output of the ESD detection circuit, for providing a discharge path between the first and second power lines when the control terminal receives the enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.