Non-volatile semiconductor memory device and multi-block erase method thereof
US7110301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2004 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Nov 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device includes memory blocks and an erase controller configured to control a multi-block erase operation where at least two of the memory blocks are simultaneously erased. According to some embodiments, after selecting and simultaneously erasing the selected memory blocks, an erase verify operation for each of the erased memory blocks is performed according to an externally provided erase verify command and block address. According to some embodiments, if a suspend command is received by the memory device while selected memory blocks are being erased, the erase operation ceases and another operation, such as a read operation, begins. When a resume command is received by the memory device, the erase operation resumes. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.