Method and system for source synchronous clocking
US7110423B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 1999 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Nov 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A source synchronous clocking synchronizes data and clock signals transmitted between an ATM layer and a link layer. The source synchronous clocking includes a source clock domain in a first layer which includes a register having a first input for receiving a data signal, a second input for receiving a clock signal, and an output; and a buffer having an input for receiving the clock signal and an output, the buffer generating a delay that is substantially equivalent to a delay through the register. The source synchronous clocking further includes a destination clock domain in a second layer which includes a register having a first input and a second input, the first input of the register of the destination clock domain being coupled to the output of the register in the source clock domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.