Method and arrangement for changing parallel clock signals in a digital data transmission
US7110484B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0083
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A changeover arrangement for the clock signals of parallel transmission connections of an assured data transmission link, wherein a clock signal is sent for the transmission paths by parallel outdoor units (OU) located in succession to a common indoor unit (IU), the clock signal is received by a corresponding set of second outdoor units, where phase locked loop signals are used to achieve the lock to the signal, and subsequent to which a second IU receives information of the mode of the phase lock. In addition, when errors are caused in the employed connection, the receiving unit selects a transmission path that has fewer errors based on mode information obtained from the outdoor unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.