Integrated circuit and package modeling
US7110930B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2002 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | May 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system and program product for creating a simplified equivalent model for an IC that can be used for detailed analysis. The equivalent model takes into consideration the effects of all the I/O placement regardless of the non-uniformity of I/O placement. The equivalent model is generated, in part, by partitioning the IC into simulation windows and converting I/Os within each simulation window to a current source having the same current change rate, and then running a simulation on this intermediate model. A current change rate observed for a simulation window is then used to convert back to actual I/Os to create the equivalent model. The equivalent model can be simulated using conventional software, e.g., SPICE, for more detailed analysis such as signal integrity, timing of I/Os and noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.