High-speed packet transfer in computer systems with multiple interfaces
US7111086B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2002 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Feb 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An initiating subsystem transfers a data set either in or out in subsets such as packets. Packet transfer is sequential, and transfer of a packet is contingent upon successful transfer of a previous packet. Actual data transfer to or from a destination, over a channel, is handled by a host interface. When an intermediate subsystem, included as an interface between the initiating subsystem and host interface, senses that the initiating subsystem wants to transfer data, it receives a first packet from the initiating system. While continuing to indicate to the initiating system that transfer of the first packet is still pending, thereby causing the initiating system to suspend further packet submission, the intermediate subsystem sends to the host interface information concerning the entire data set to be transferred. When the entire data set is transferred, the intermediate subsystem emulates successful packet-wise transfer to the initiating subsystem. In the preferred embodiment of the invention, the initiating subsystem is a virtual machine, the intermediate subsystem is a virtual machine monitor, and the packets are created according to the USB protocol. Mechanisms are included to…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.