Generating isolated bus cycles for isolated execution
US7111176B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is a method and apparatus to generates an isolated bus cycle for a transaction in a processor. A configuration storage contains configuration parameters to configure a processor in one of a normal execution mode and an isolated execution mode. An access generator circuit generates an isolated access signal using at least one of the isolated area parameters and access information in the transaction. The isolated access signal is asserted when the processor is configured in the isolated execution mode. A bus cycle decoder generates an isolated bus cycle corresponding to a destination in the transaction using the asserted isolated access signal and the access information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.