Built-in debug feature for complex VLSI chip
US7111199B2 · kind B2 · utility
2Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2002 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Dec 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318516
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus comprising (i) a first circuit configured to generate one or more node signals at one or more internal nodes and (ii) a second circuit configured to present one or more of the node signals and a trigger signal in response to one or more control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.