Methods and systems of using result buffers in parity operations
US7111227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2003 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Apr 26, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1057
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A disk controller includes memory that is accessible by both a microprocessor and hardware parity logic. Parity-related operations are identified by scenario, and parity coefficient subsets are stored in a memory table for each different parity-related calculation scenario. To perform a particular parity-related operation, the microprocessor determines the operation's scenario and identifies the corresponding coefficient subset. The hardware parity logic is then instructed to perform the appropriate parity computation, using the identified coefficient subset. In one embodiment, parity segments are calculated by a parity segment calculation module that is embodied as an application specific integrated circuit (ASIC). The ASIC includes one or more result buffers for holding intermediate computation results, one or more mathematical operator components configured to receive data segments and coefficients associated with the data segments and operate on them to provide intermediate computation results that can be written to the one or more result buffers, and one or more feedback lines. The feedback lines are coupled between an associated result buffer and an associated mathematical op…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.