Patent · US Expired

Electronic circuit design analysis system

US7111275B2 · kind B2 · utility

3Cited by

1References

31Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Thaddeus Chen · Wappingers Falls, US
Zhaoqing Chen · Poughkeepsie, US
Hubert Harrer · Böblingen, DE
Jan Hoffman · Berlin, DE
Susan Marie Karwoski · Rochester, US
Joonsuk Park · San Diego, US
Stephen White · Minnesota City, US
John W. Zack · Rochester, US

Key dates

Filing date	Aug 28, 2003
Grant date	Sep 19, 2006
Priority date	—
Expiry date	Sep 29, 2024

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/33
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method, apparatus and program product generate package files that are separately stored and selectively combined to generate a net file suited for system simulation and analysis. Selective combination of the package files using respective reference connections of each package enables focused and efficient modeling of design performance characteristics.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.