Request and completion queue load balancing
US7111301B1 · kind B1 · utility
2Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2001 |
| Grant date | Sep 19, 2006 |
| Priority date | — |
| Expiry date | Sep 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a request count in response to a request head pointer and a request tail pointer. The second circuit may be configured to generate a completion count in response a completion head pointer and a completion tail pointer. The third circuit may be configured to prioritize an interrupt in response to the request and completion counts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.