Stacked capacitor having parallel interdigitized structure for use in thin film transistor liquid crystal display
US7112820B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2003 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | May 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/00
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A capacitor structure includes a first conductive layer, a first insulating layer disposed on a substrate in sequence, a second conductive layer disposed on portions of the first insulating layer, a second insulating layer disposed on the second conductive layer and the first insulating layer, a third conductive layer disposed on portions of the second insulating layer, a third insulating layer disposed on the third conductive layer and the second insulating layer, and a fourth conductive layer disposed on the third insulating layer. The third conductive layer and the fourth conductive layer are electrically connected to the first conductive layer and the second conductive layer through at least one first contact hole adjacent to the second conductive layer and at least one second contact hole, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.