Super lattice modification of overlying transistor
US7112830B2 · kind B2 · utility
34Cited by
64References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 25, 2003 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Nov 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
Abstract
The invention provides a device having a substrate, a buffer region positioned upon the substrate, wherein the buffer region has an upper buffer region and a lower buffer region, a heterojunction region positioned upon the buffer region, and a superlattice positioned between the lower buffer region and the upper buffer region, wherein the device is configured to function as a heterojunction field effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.