Physical layers
US7112990B2 · kind B2 · utility
2Cited by
3References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2004 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Jan 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/0013
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Improvements to the physical layer are provided, for example a test circuit that does not introduce further skew into critical clock signals. A boundary scan test circuit is also provided used to isolate an integrated circuit for applying test vectors or circuit brand connections to test the integrity thereof. A bias voltage generator for a voltage controlled delay line (VCDL) is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.