Capacitance multiplier circuit exhibiting improving bandwidth
US7113020B2 · kind B2 · utility
5Cited by
4References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 25, 2004 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Mar 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/405
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A monolithic capacitance multiplication circuit serves to reduce the required die area when larger capacitance values are needed such as in filter and loop frequency compensation circuits. A current mirror/cascoding device arrangement reduces the effective series resistance of the multiplier capacitor. As a result, the multiplier topology exhibits improved bandwidth over prior art capacitance multiplier circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.