Capacitance multiplier
US7113022B2 · kind B2 · utility
1Cited by
5References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2004 |
| Grant date | Sep 26, 2006 |
| Priority date | — |
| Expiry date | Oct 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/483
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A capacitance multiplier includes a self-biasing active load for generating a stable bias voltage without a separate current bias. In addition, the capacitance multiplier includes a cascode load within a multiplying section for increasing the output resistance and in turn the charging/discharging efficiency. Furthermore, the capacitance multiplier is implemented with a plurality of multiplying paths to reduce effects of noise for more stable generation of the multiplied capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.